Number of Channels per Chip | 2 |
---|---|
PCB changed | 14 |
Maximum Propagation Delay Time @ Maximum CL (ns) | 21@6V|125@2V|25@4.5V |
Number of Elements per Chip | 2 |
ECCN (US) | EAR99 |
Minimum Operating Temperature (°C) | -55 |
Maximum Operating Temperature (°C) | 125 |
Supplier Package | SOP |
Maximum High Level Output Current (mA) | -5.2 |
Process Technology | CMOS |
Absolute Propagation Delay Time (ns) | 210 |
Propagation Delay Test Condition (pF) | 50 |
Logic Function | JK-Type |
Package Height | 1.65(Max) |
Triggering Type | Negative-Edge |
Number of Element Outputs | 1 |
Polarity | Inverting/Non-Inverting |
Maximum Operating Supply Voltage (V) | 6 |
RoHS Status | Supplier Unconfirmed |
Set/Reset | Reset |
Number of Element Inputs | 2 |
Package Length | 8.75(Max) |
Standard Package Name | SOP |
Maximum Low Level Output Current (mA) | 5.2 |
Pin Count | 14 |
Mounting | Surface Mount |
Input Signal Type | Single-Ended |
Bus Hold | No |
Lead Shape | Gull-wing |
Packaging | Tube |
Part Status | Obsolete |
Typical Operating Supply Voltage (V) | 5|2.5|3.3 |
Logic Family | HC |
Package Width | 4(Max) |
Maximum Quiescent Current (mA) | 0.002 |
Minimum Operating Supply Voltage (V) | 2 |